differential clock buffer/dri ver ddr400 and ddr333-compliant cy28352-400 rev 1.0, november 28, 2006 page 1 of 7 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? supports 333-mhz and 400-mhz ddr sdram ? 60?273-mhz operating frequency ? phase-locked loop (pll) clock distribution for double data rate synchronous dram applications ? distributes one clock input to six differential outputs ? external feedback pin fbin is used to synchronize output to clock input ? conforms to ddr i specification ?spread aware ? for electromagnetic interference (emi) reduction ? 28-pin ssop package description this pll clock buffer is designed for 2.6v dd and 2.6av dd operation and differential output levels. this device is a zero delay buff er that distributes a clock input clkin to six differential pair s of clock outputs (clkt[0:5], clkc[0:5]) and one feedback clock output fbout. the clock outputs are controlled by the input clock clkin and the feedback clock fbin. the two-line serial bus can set each output clock pair (clkt[0:5], clkc[0:5]) to the hi-z state. when av dd is grounded, the pll is turned off and bypassed for test purposes. the pll in this device uses the input clock clkin and the feedback clock fbin to provide high-performance, low-skew, low-jitter output differential clocks. block diagram pin configuration 28 pin ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd clkt5 nc fbout clkt3 clkc3 gnd nc fbin clkc5 clkc4 clkt4 vdd sdata clkc0 vdd clkin avdd vdd clkt2 clkc2 agnd nc clkt0 clkt1 clkc1 gnd sclk cy28352-400 serial interface logic sdata sclk clkt0 fbout clkc0 clkt1 clkc1 clkt2 clkc2 clkc3 clkt3 clkc4 clkt4 clkc5 clkt5 pll fbin clkin avdd 10
cy28352-400 rev 1.0, november 28, 2006 page 2 of 7 zero delay buffer when used as a zero delay buffer the cy28352-400 will likely be in a nested clock tree application. for these applications the cy28352-400 offers a clock input as a pll reference. the cy28352-400 can then lock onto the reference and translate with near zero delay to low-skew outputs. for normal operation, the external feedback input, fbin, is connected to the feedback output, fbout. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll wo rks to align the output edge with the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when a vdd is strapped low, the pll is turned off and bypassed for test purposes. power management the individual output enable/disable control of the cy28352-400 allows the user to implement unique power management schemes into the design. outputs are three-stated when disabled through the two-line interface as individual bits are set low in byte0 and byte1 registers. the feedback output fbout cannot be disabled via two line serial bus. the enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial ?runt? clocks. pin description [1] pin number pin name i/o pin description electrical characteristics 8clkini complementary clock input . input 20 fbin i feedback clock input . connect to fbout for accessing the pll. input 2,4,13,17,24, 26 clkt(0:5) o clock outputs differential outputs 1,5,14,16,25, 27 clkc(0:5) o clock outputs 19 fbout o feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at th is output will control input reference/output clo cks phase relationships. output 7sclki serial clock input . clocks data at sdata into the internal register. data input for the two line serial bus 22 sdata i/o serial data input . input data is clocked to the internal register to enable/disable individual outputs. this provides flexibility in power management. data input and output for the two line serial bus 3,12,23 v dd 2.6v power supply for logic 2.6v nominal 10 av dd 2.6v power supply for pll 2.6v nominal 6,15,28 gnd ground 11 agnd analog ground for pll 9, 18, 21 nc not connected function table inputs outputs pll avdd clkin clkt(0:5) [2] clkc(0:5) [2] fbout gnd l l h l bypassed/off gnd h h l h bypassed/off 2.5v l l h l on 2.5v h h l h on 2.5v <20 mhz hi-z hi-z hi-z off notes: 1. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (< 0.2?). if these bypass capacitors are not close to the p ins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. each output pair can be three-stated via the two-line serial interface.
cy28352-400 rev 1.0, november 28, 2006 page 3 of 7 serial control registers following the acknowledge of t he address byte, two additional bytes must be sent: ? command code byte ? byte count byte. byte0: output register1 (1 = enable, 0 = disable) bit @pup pin# description 7 1 2, 1 clkt0, clkc0 6 1 4, 5 clkt1, clkc1 51?reserved 41?reserved 3 1 13, 14 clkt2, clkc2 2 1 26, 27 clkt5, clkc5 11?reserved 0 1 24, 25 clkt4, clkc4 byte1: output register 2 (1 = enable, 0 = disable) bit @pup pin# description 71?reserved 6 1 17, 16 clkt3, clkc3 50?reserved 40?reserved 30?reserved 20?reserved 10?reserved 00?reserved byte2: test register 3 bit @pup pin# description 7 1 ? 0 = pll leakage test, 1 = disable test 6 1 ? reserved 5 0 ? reserved 4 0 ? reserved 3 0 ? reserved 2 0 ? reserved 1 0 ? reserved 0 0 ? reserved
cy28352-400 rev 1.0, november 28, 2006 page 4 of 7 absolute maximum conditions [3] input voltage relative to v ss :...............................v ss ? 0.3v input voltage relative to v dd or av dd : ............... v dd + 0.3v storage temperature: ................................ ?65 c to + 150 c operating temperature:................................ ?40 c to +85 c maximum power supply: ................................................ 3.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc electrical specifications [4] parameter description condition min. typ. max. unit v dd, a vdd supply voltage operating 2.5 ? 2.7 v v il input low voltage sdata, sclk ? ? 1.0 v v ih input high voltage sdata, sclk 2.2 ? ? v v il input voltage low clkin, fbin ? ? 0.3v dd v v ih input voltage high clkin, fbin 0.6v dd ??v i in input current v in = 0v or v in = v dd , clkin, fbin ?10 ? 10 a v ol output low voltage v dd = 2.375v, i ol = 12 ma ? 0.6 v v oh output high voltage v dd = 2.375v, i oh = ?12 ma 1.7 ? ? v v out output voltage swing [5] 1.1 ? v dd ? 0.4 v v oc output crossing voltage [6] (v dd /2) ? 0.15 v dd /2 (v dd /2) + 0.15 v i oz high-impedance output current v o = gnd or v o = v dd ?10 ? 10 a i ddq dynamic supply current [7] all v dd , fo = 273 mhz ?235 300ma i dstat static supply current ? ? 1 ma i dd pll supply current a vdd only ? 9 12 ma c in input pin capacitance ? 4 6 pf ac electrical specifications [7, 9] parameter description condition min. typ. max. unit fclk operating clock frequency a vdd , v dd = 2.5v to 2.7v 60 ? 273 mhz tdc input clock duty cycle 40 ? 60 % tlock maximum pll lock time ? ? 100 s d tyc duty cycle 60 mhz to 170 mhz 49 50 51 % 170 mhz to 273 mhz 48 ? 52 % tr / tf output clocks slew rate 20% to 80% of v od 1? 2.5v/ns tpzl, tpzh output enable time [10] (all outputs) ?3 ns tplz, tphz output disable time [10] (all outputs) ?3 ns notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 4. unused inputs must be held high or low to prevent them from floating. 5. for load conditions, see figure 7 . 6. the value of v oc is expected to be |vtr + vcp|/2. in case of each clock directly terminated by a 120 resistor. see figure 7 . 7. all outputs switching loaded with 16 pf in 60 environment. see figure 7 . 8. parameters are guaranteed by design and char acterization. not 100% tested in production. 9. pll is capable of meeting t he specified parameters while supporting ssc synt hesizers with modulati on frequency between 30 khz and 33.3 khz, with a down spread of ?0.5%. 10. refers to transition of non-inverting output. 11. all differential input and output terminals are terminated with 120 /16 pf as shown in figure 7 . 12. period jitter and half-per iod jitter specifications ar e separate, and must be met independen tly of each other.
cy28352-400 rev 1.0, november 28, 2006 page 5 of 7 parameter measurement information tccj cycle-to-cycle jitter [12] f > 66 mhz ?75 ? 75 ps tjit(h-per) half-period jitter [12] f > 66 mhz ?75 ? 75 ps tplh low-to-high propagation delay, clkin to clkt[0:5] 1.5 3.5 6 ns tphl high-to-low propagation delay, clkin to clkt[0:5] 1.5 3.5 6 ns tskew any output to any output skew [11] ? ? 100 ps tphase phase error [11] ?150 ? 150 ps tphasej phase error jitter f > 66 mhz ?50 ? 50 ps ac electrical specifications (continued) [7, 9] parameter description condition min. typ. max. unit t ( ? ) n = n=n t ( ? ) n (n is large number of samples) 1 t ( ? ) n t ( ? ) n+1 clkin fbin 1.25v 1.25v 1.25v 1.25v figure 1. static phase offset t d( ? ) t d( ? ) t ( ? ) t ( ? ) t d( ? ) t d( ? ) clkin fbin 1.25v 1.25v figure 2. dynamic phase offset clkt[0:5], fbout tsk(o) clkc[0:5] clkt[0:5], fbout clkc[0:5] figure 3. output skew
cy28352-400 rev 1.0, november 28, 2006 page 6 of 7 t c(n) 1 f(o) t jit(hper) = t c(n) - 1 fo clkt[0:5], fbout clkc[0:5] clkt[0:5], fbout clkc[0:5] figure 4. period jitter 1 f(o) t (hper_n+1) t (hper_n) t jit(hper) = t hper(n) - 1 2x fo clkt[0:5], fbout clkc[0:5] figure 5. half-period jitter t j it(cc) = t c(n) -t c(n+1) clkt[0:5], fbout clkc[0:5] t c(n) t c(n) figure 6. cycle-to-cycle jitter clkt t pcb t pcb clkc 110 measurement point 16 pf measurement point 16 pf clkin fbin fbout 50 50 figure 7. differential signal using direct termination resistor
rev 1.0, november 28, 2006 page 7 of 7 cy28352-400 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions part number package type product flow cy28352oc?400 28-pin ssop commercial, 0 to 70 c cy28352oc?400t 28-pin ssop?tape and reel commercial, 0 to 70 c cy28352oi?400 28-pin ssop industrial, ?40 to 85 c cy28352oi?400t 28-pin ssop?tape and reel industrial, ?40 to 85 c 28-lead (5.3 mm) shrunk small outline package o28 51-85079-*c
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